Integrated circuit device having a resistor and method of manufacturing the same

ABSTRACT

In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of prior application Ser.No. 13/324,035, filed on Dec. 13, 2011, in the United States Patent andTrademark Office, which claims the benefit of priority under 35 U.S.C.§119 from Korean Patent Application No. 10-2011-0002546 filed on Jan.11, 2011, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Example embodiments relate to an integrated circuit device and a methodof manufacturing the same, and more particularly, to an integratedcircuit device including a resistor and a method of manufacturing thesame.

2. Description of the Related Art

As the semiconductor industry has made rapid progress, integratedcircuit devices have been utilized for many electronic instruments invarious industrial fields. The integrated circuit device generallyincludes a great number of transistors, diodes, capacitors and resistorsthat are highly integrated therein, and thus an overall resistance ofthe integrated circuit device needs to be variable in accordance withrequirements of the electronic instruments including the integratedcircuit device.

In conventional integrated circuit devices, the resistor has an electricresistance greater than that of wiring structures and thus low-resistivematerials for the wiring structure are insufficient for the resistor. Inaddition, the resistors are generally formed simultaneously with thediodes and the transistors and no additional process is provided justfor the resistors in view of process efficiency of the manufacturingprocess.

For those reasons, the resistor of the integrated circuit devices may beformed on the device isolation layer simultaneously with the gatestructure of the transistor. That is, the gate structure may be formedon an active region of a substrate and the transistor may be formed onthe device isolation layer simultaneously with the gate structure in thesame process. Since electric resistance of polysilicon is easilycontrolled by doping various impurities, both of the gate structure andthe resistor generally include polysilicon.

A doped polysilicon pattern is usually used as the resistor of theintegrated circuit device and a conductive connector is connected withthe resistor and external wirings. Thus, the connector compriseslow-resistive metals so as to reduce contact resistance at a boundaryarea of the resistor and the connector.

However, when polysilicon of the resistor and the metal of the connectormake direct contact with each other, a plurality of voids is generatedat the boundary area of the connector and the resistor due to thesilicidation process of the polysilicon and the metal. Thus, a contactresistance of the resistor is rapidly increased and the resistor and thewiring tend to be electrically disconnected from each other due to thevoids. Since it is widely known that the contact resistance has acritical effect on an overall sheet resistance of the resistor, thevariation of the contact resistance caused by the silicidation betweenthe resistor and the connector necessarily leads to the variation of theoverall resistance of the resistor.

When programming, erasing or reading data in flash memory devices, areference voltage is usually applied to a reference cell transistor by areference cell operator and the reference cell operator conventionallyneeds the resistor. Thus, the large resistance variation of the resistornecessarily leads to an unstable operation of the reference celloperator, thereby severely deteriorating the reliability of the flashmemory device. Recently, the resistance variation of the resistor istend to increase due to the reduction of critical dimension (CD) ofsemiconductor chips and thus the operation reliability of the integratedcircuit devices is tend to be deteriorated.

Accordingly, there is still a need for an improved resistor forintegrated circuit devices in which the variation of the contactresistance and the sheet resistance are minimized and thus the operationreliability of the integrated circuit device is sufficiently improved.

SUMMARY OF THE INVENTION

Example embodiments of the present inventive concept provide anintegrated circuit device in which a contact resistance of a resistor isminimized.

Other example embodiments of the present inventive concept provide amethod of manufacturing the above integrated circuit device.

Additional aspects and advantages of the present general inventiveconcept will be set forth in part in the description which follows and,in part, will be obvious from the description, or may be learned bypractice of the general inventive concept.

According to some example embodiments, there is provided a method ofmanufacturing an integrated circuit device. A substrate may be preparedto have an active region defined by a device isolation layer. A resistorpattern may be formed on the device isolation layer. The resistorpattern may include a resistor body positioned in a recess portion ofthe device isolation layer and at least a connector making contact withthe resistor body and positioned on the device isolation layer aroundthe recess portion. The connector may include a metal silicide patternhaving electric resistance lower than that of the resistor body at anupper portion thereof. A gate pattern may be formed on the active regionof the substrate. The gate pattern may include the metal silicidepattern at an upper portion thereof. A resistor interconnection may beformed to make contact with the connector of the resistor pattern.

A plurality of the gate patterns may be formed on a cell area of thesubstrate in which a plurality of cell transistors is formed and on aperipheral circuit portion of a peripheral area of the substrate inwhich a plurality of peripheral transistors electrically connected tothe cell transistor is formed, and the resistor pattern is formed on aresistor portion of the peripheral area of the substrate simultaneouslywith the gate pattern.

The resistor pattern may be exemplarily formed as follows: The deviceisolation layer may be on a field region of the substrate and a tunnelinsulation pattern and a floating gate pattern on the active region ofthe substrate in such a manner that the device isolation layer and thetunnel insulation pattern and a floating gate pattern are shaped into aline and a sidewall of the floating gate pattern is exposed over thedevice isolation layer in the cell area and the device isolation layeris formed into a bulk shape in the resistor portion of the peripheralarea of the substrate. Then, a dielectric layer and a first conductivelayer may be formed on the floating gate pattern and the deviceisolation layer. The bulk-shaped device isolation layer at the resistorportion of the peripheral area of the substrate may be partially removedwhile partially exposing the floating gate pattern on the active regionof the substrate, thereby forming the recess portion on the bulk-shapeddevice isolation layer. A second conductive layer may be formed on thecell area and the peripheral area of the substrate along a surfaceprofile thereof. The second conductive layer, the first conductive layerand the dielectric layer may be patterned, thereby forming a preliminarygate pattern on the active region of the substrate and forming apreliminary resistor pattern on the bulk-shaped device isolation layer.The preliminary resistor pattern may include a preliminary resistor bodyat a bottom of the recess portion and a preliminary connector on thebulk-shaped device isolation pattern around the recess portion thereof.A metal silicide pattern may be formed on the preliminary gate patternand the preliminary resistor pattern, so that the resistor pattern onthe resistor portion of the peripheral area of the substrate may beformed simultaneously with the gate pattern on the active region of thesubstrate.

The device isolation layer may be formed as follows. The substrate onwhich the tunnel insulation layer and the floating gate layer arestacked may be etched off by a self-aligned process, thereby forming atrench in the field region of the substrate simultaneously with thetunnel insulation pattern and the floating gate pattern defined by thetrench. Then, the trench may be filled up with insulation materials,thereby forming the device isolation layer in the trench. An upperportion of the device isolation layer may be partially removed in thecell area of the substrate, thereby exposing the sidewall of thefloating gate pattern over the device isolation layer in the cell areaof the substrate.

The bulk-shaped device isolation layer may be removed as follows. Afirst mask pattern may be formed on the first conducive layer. The firstmask pattern may include a plurality of openings through which the firstconductive layer is partially exposed on the active region and theresistor portion of the peripheral area of the substrate, respectively.The first conductive layer, the dielectric layer and the bulk-shapeddevice isolation layer may be partially removed by a first etchingprocess using the first mask pattern as an etching mask at the resistorportion of the peripheral area while simultaneously removing the firstconductive layer and the dielectric layer at the active region of thesubstrate by the first etching process, so that the recess portion maybe formed on the bulk-shaped device isolation layer at the resistorportion of the peripheral area and the floating gate pattern may bepartially exposed at the active region of the substrate.

The first mask pattern may include a first opening through which thefloating gate pattern corresponding to a string selection transistor isexposed in the cell area, a second opening through which the floatinggate pattern corresponding to the peripheral transistor is exposed inthe peripheral circuit portion of the peripheral area and a thirdopening through which a central portion of the bulk-shaped deviceisolation layer is exposed.

The second conductive layer may be formed into a control gate of a stackgate pattern together with the first conducive layer in the cell areawhile the second conductive layer making contact with the floating gatepattern through the first opening is formed into the string selectiontransistor and the second conductive layer making contact with thefloating gate pattern through the second opening is formed into theperipheral transistor.

The second conductive layer, the first conductive layer and thedielectric layer may be patterned as follows: A second mask pattern maybe formed on the second conductive layer. A dry etching process may besequentially performed against the second conductive layer, the firstconductive layer and the dielectric layer using the second mask patternas an etching mask, thereby forming the preliminary gate pattern and thepreliminary resistor pattern.

The metal silicide pattern may be formed as follows. A protection layermay be formed to cover the preliminary gate pattern and the preliminaryresistor pattern. The protection layer may be planarized until thepreliminary gate pattern and the preliminary resistor pattern areexposed, thereby forming a protection pattern form which a secondconductive pattern is protruded. A metal layer may be formed on theprotection pattern such hat the second conductive pattern is coveredwith the metal layer. A heat treatment may be performed to the metallayer, thereby forming the metal silicide layer on the second conductivepattern.

Before forming the protection layer, spacers may be further formed onsidewalls of the preliminary gate pattern and the preliminary resistorpattern. An etch stop layer may be further formed on the preliminarygate pattern, the preliminary resistor pattern, the tunnel insulationlayer and the etch stop layer.

The protection layer may include tetra ethyl ortho silicate deposited byplasma enhanced chemical vapor deposition process (PETEOS). Theprotection layer may be planarized by one of a chemical mechanicalpolishing (CMP) process, a chemically enhanced polishing (CEP) processand an etch-back process.

The metal layer may include at least a material selected from the groupconsisting of tungsten (W), nickel (Ni), cobalt (Co), titanium (Ti),tantalum (Ta) and combinations thereof.

The resistor interconnection may be formed as follows: An insulationinterlayer may be formed on the protection pattern and the metalsilicide pattern and the insulation interlayer may be patterned tothereby form an opening through which the metal silicide pattern on theconnector is exposed. A first conductive pattern may be formed in theopening such that the first conductive pattern may make contact with themetal silicide pattern of the connector.

A second conductive pattern may be further formed to make contact withthe active region of the substrate through the insulation interlayer.The second conductive pattern may be formed simultaneously with thefirst conductive pattern.

According to some example embodiments, there is provided an integratedcircuit device including a resistor pattern having a metal silicidepattern to thereby reduce a contact resistance. The integrated circuitdevice includes a substrate having an active region defined by a deviceisolation layer, a resistor pattern formed on the device isolationlayer, a gate pattern formed on the active region of the substrate and aresistor interconnection making contact with the connector of theresistor pattern. The resistor pattern may include a resistor bodypositioned in a recess portion of the device isolation layer and atleast a connector making contact with the resistor body and positionedon the device isolation layer around the recess portion. The connectormay include a metal silicide pattern having an electric resistance lowerthan that of the resistor body at an upper portion thereof. The gatepattern may include the metal silicide pattern at an upper portionthereof.

The connector may include a stack structure in which a dielectricpattern, a first conductive pattern, a second conductive pattern and themetal silicide pattern are sequentially stacked and the resistor bodyincludes the second conductive pattern.

The first conductive pattern may include carbon (C)-doped polysiliconand the second conductive pattern includes phosphor (P)-dopedpolysilicon.

The second conductive pattern may be continuously arranged across theresistor body and the connector and the connector and the resistor bodyhas a stepped portion of about 800 Å to about 1,000 Å.

The gate pattern may include a tunnel insulation layer, a floating gatepattern, the dielectric pattern, the first and the second conductivepatterns that are sequentially stacked on the cell area of thesubstrate.

The resistor pattern for applying a reference voltage to celltransistors may be provided with the bulk device isolation layer in sucha configuration that the resistor body is arranged in the recess of thebulk device isolation layer and the connector is arranged around therecess of the bulk device isolation layer, so that the resistor patternmay have a stepped portion between the resistor body and the connector.Particularly, the metal silicide may be arranged at the upper portion ofthe connector of the resistor pattern. Thus, a contact resistance Rcbetween the connector and the resistor interconnection may besufficiently reduced without any deterioration of a sheet resistance Rsof the resistor body. Accordingly, the electrical resistance of theresistor pattern may be reduced and become stable, and thus thereference voltage may be applied to the cell transistors with highreliability.

The foregoing and/or other aspects and utilities of the present generalinventive concept may also be achieved by providing a method ofmanufacturing an integrated circuit device, the method including formingone or more device isolation layers on a cell area and a peripheral areaof a substrate, forming a resistor pattern having a resistor body havinga first electric resistance and a connector having a second electricresistance lower than the first electric resistance, on the deviceisolation layers of a resistor portion of the peripheral area of thesubstrate, and forming a resistor interconnection to contact theconnector of the resistor pattern to reduce a contact resistancetherebetween.

The method may further include forming one or more gate patterns onactive regions of the cell area of the substrate, and the forming of thedevice isolation layers in the cell area may include forming the deviceisolation layers in field regions of the cell area between the adjacentactive regions.

The forming of the gate patterns may include forming a floating gatepattern of the gate pattern to be disposed between the device isolationlayer such that an upper portion of the floating gate pattern of thegate pattern is exposed from an upper portion of one or more the deviceisolation layers.

The forming of the one or more device isolation layers on the peripherallayer of the substrate may include forming a recess portion and aprotrusion portion in the respective device isolation layers, formingthe resistor body on the recess portion and the protrusion portion; andforming the connector on the protrusion portion to have a depth ofrecess with the resistor body in the recess portion.

The foregoing and/or other aspects and utilities of the present generalinventive concept may also be achieved by providing an integratedcircuit device including one or more device isolation layers formed on acell area and a peripheral area of a substrate, a resistor patternhaving a resistor body having a first electric resistance and aconnector having a second electric resistance lower than the firstelectric resistance, formed on the device isolation layers of a resistorportion of the peripheral area of the substrate, and a resistorinterconnection formed to contact the connector of the resistor patternto reduce a contact resistance therebetween.

One or more gate patterns may be formed on active regions of the cellarea of the substrate, and the device isolation layers are formed infield regions of the cell area between the adjacent active regions.

A floating gate pattern of the gate pattern may be formed to be disposedbetween the device isolation layers such that an upper portion of thefloating gate pattern of the gate pattern is exposed from an upperportion of one or more the device isolation layers.

A recess portion and a protrusion portion may be formed in therespective device isolation layers such that the resistor body is on therecess portion and the protrusion portion, and the connector is formedon the protrusion portion to have a depth of recess with the resistorbody in the recess portion.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the present generalinventive concept will become apparent and more readily appreciated fromthe following description of the embodiments, taken in conjunction withthe accompanying drawings of which:

FIG. 1 is a plan view illustrating an integrated circuit device inaccordance with an example embodiment of the present inventive concept;

FIG. 2A is a cross-sectional view along a line I-I′ of FIG. 1;

FIG. 2B is a cross-sectional view along a line II-II′ of FIG. 1;

FIG. 2C is a cross-sectional view along a line III-III′ of FIG. 1;

FIGS. 3A to 12C are cross-sectional view illustrating a method ofmanufacturing the integrated circuit device of FIG. 1;

FIG. 13 is a view illustrating an integrated circuit system includingthe integrated circuit device of FIG. 1; and

FIG. 14 is a view illustrating an electronic instrument including theintegrated circuit system of FIG. 13.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the embodiments of the presentgeneral inventive concept, examples of which are illustrated in theaccompanying drawings, wherein like reference numerals refer to the likeelements throughout. The embodiments are described below in order toexplain the present general inventive concept while referring to thefigures. The present invention may, however, be embodied in manydifferent forms and should not be construed as limited to the exampleembodiments set forth herein. Rather, these example embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the present invention to those skilled in theart. In the drawings, the sizes and relative sizes of layers and regionsmay be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of thepresent invention. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized example embodiments (and intermediate structures). As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, example embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, example embodiments of an integrated circuit device will beexplained in detail with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating an integrated circuit device inaccordance with an example embodiment of the present inventive concept.FIG. 2A is a cross-sectional view along a line I-I′ of FIG. 1 and FIG.2B is a cross-sectional view along a line II-II′ of FIG. 1. FIG. 2C is across-sectional view along a line III-III′ of FIG. 1. Hereinafter, anintegrated circuit device including one or more flash memory deviceswill be disclosed as an illustrative of example embodiments of thepresent inventive concept but is not to be construed as limitingthereof. Thus, the present inventive concept is also applicable to otherintegrated circuit devices including various semiconductor devices.

Referring to FIGS. 1 and 2A to 2C, the integrated circuit device 1000 inaccordance with an example embodiment of the present inventive conceptmay include a gate pattern 180 and a resist pattern 190 formed on asubstrate 101. The substrate 101 may include an active region A definedby a device isolation layer 102 disposed in a field region, and the gatepattern 180 may be positioned on the active region A of the substrate101 and the resistor pattern 190 may be positioned on the deviceisolation layer 102. The resistor pattern 190 may include a resistorbody 191 and a connector 192. The resistor body 191 may have a steppedportion. A metal silicide pattern 115 c may be arranged on upperportions of the gate pattern 180 and the connector 192 of the resistorpattern 190.

The substrate 101 may include a semiconductor substrate such as a waferand divided into the active region A on which conductive structures,such as transistors, may be arranged and the field region F on which thedevice isolation layer may be arranged.

A plurality of cell transistors may be arranged in a cell area 101 a ofthe substrate 101 in a matrix shape. A data operation, such as theprogramming, an erasing operation, and a reading operation may beperformed in the cell transistors. A plurality of peripheral transistorsmay be arranged in a peripheral area 101 b of the substrate 101. Forexample, the peripheral transistors may be provided in a driving circuitto drive the cell transistors and a ground circuit to provide potentialof an electrical ground to the cell transistors. The peripheral area 101b of the substrate 101 may include a peripheral circuit portion 101 b 1in which the peripheral transistors may be arranged and a resistorportion 101 b 2 in which the resistor pattern 190 may be arranged. Theresistor pattern 190 may be connected to the driving circuit and thuscontrol a reference voltage to be applied to the cell transistors.

In the present example embodiment, the active region A may have a shape,for example, a line shape extending in a first direction x in the cellarea 101 a of the substrate 101. A plurality of the gate patterns 180for a cell transistor may be arranged in the active region A along thefirst direction x and be spaced apart from each other by a cell gapdistance. A pair of source and drain electrodes (not illustrated) may bearranged at both sides of each gate pattern. Each of the gate patternsmay also be connected in series along a second direction y substantiallyperpendicular to the first direction x to thereby form a plurality oflines extending in the second direction y. The lines may function asstring selection lines (SSLs), word lines (WLs) and ground selectionlines (GSLs) for a flash memory device.

A plurality of the peripheral transistors may be arranged in theperipheral area 101 b of the substrate 101. The peripheral transistorsmay be electrically connected to a line to thereby form a peripheralconductive line CL that may be at least one of the SSLs, WLs and GSLs.Thus, the peripheral conductive line CL may include a gate line totransfer data signals to the word line WL. The peripheral transistorsmay be spaced apart from one another by a peripheral gap distancegreater than the cell gap distance of the cell transistors, and theperipheral conductive line CL may extend in any directions according todevice and process requirements.

A device isolation layer 102 may be a bulk type device isolation layerto be provided in the resistor area 101 b 2 of the peripheral area 101b. A recess, such as a line-shaped recess, may be provided with thedevice isolation layer 102 as illustrated in FIG. 2C. The resistorpattern 190 may be positioned on the device isolation layer 102 along asurface profile of the line-shaped recess. The resistor pattern 190 mayinclude the resistor body 191 positioned on a bottom and a sidewall ofthe recess and the connector 192 positioned on both end portions of theresistor body 191. External wirings may make contact with the connector192 and thus external signals may be applied from an external device tothe resistor pattern 190 though the external wirings and the connector192.

The gate pattern 180 may include a stack gate pattern in which a tunnelinsulation pattern 110 c, a floating gate pattern 111 c, a dielectricpattern 112 c, a control gate pattern having a first and a secondconductive pattern 113 c and 114 c and a metal silicide pattern 115 cmay be sequentially stacked on the active region A of the substrate 101.Particularly, the transistors for the SSL may not include the dialecticpattern 112 c and the first conductive pattern 114 c. Thus, the floatinggate pattern 111 c and the second conductive pattern 114 c may makedirect contact with each other in the transistor for the SSL.

The tunnel insulation pattern 110 c and the floating gate pattern 111 cmay be shaped into a line extending in the first direction x, and thedielectric pattern 112 c, the first conductive pattern 113 c and thesecond conductive pattern 114 c may be shaped into a line extending inthe second direction y.

The device isolation layer 102 may include an insulation layer filledinto a trench (not illustrated) around the active region A and thus theactive region A of the substrate 101 may be isolated from one another bythe device isolation layer 102. An upper portion of the isolation layermay be removed in such a way that a sidewall of the floating gatepattern 111 c may be exposed to a field region F of the substrate 101 asillustrated in FIG. 2B. The device isolation layer 102 disposed in thecell area 101 a may also be shaped into a line extending in the firstdirection x in parallel with the active region A in such a configurationthat the line-shaped active region A and the line-shaped deviceisolation layer 102 may be arranged alternately with each other alongthe second direction y.

The device isolation layer 102 of the peripheral area 101 b may beshaped into various shapes according to the device and processrequirements of the integrated circuit device 1000. For example, aline-shaped device isolation layer may be positioned at the peripheralcircuit portion 101 b 1 of the peripheral area 101 b and thus theperipheral conductive lines CL may be electrically isolated from oneanother by the line-shaped device isolation layer. The device isolationlayer 102, such as a bulk-type device isolation, layer may be positionedat the resistor portion 101 b 2 of the peripheral area 101 b and thusthe resistor pattern 190 may be positioned on the bulk-type deviceisolation layer.

For example, the resistor pattern 190 of the resistor portion 101 b 2 ofthe substrate 101 may be shaped into a line extending in the firstdirection x and may have a stepped portion between the resistor body 191and the connector 192 due to the recess of the bulk device isolationlayer 102.

A plurality of the line-shaped recesses may be provided on an uppersurface of the bulk-type device isolation layer along the firstdirection x and each of the recesses may have a depth D from the uppersurface of the bulk-type device isolation layer. Thus, the bulk-typedevice isolation layer may include a recess portion 104 and a protrusionportion 105 around the recess portion 104. The resistor body 191 of theresistor pattern 190 may be positioned in the recess portion 104 and theconnector 192 of the resistor pattern 190 may be positioned on theprotrusion portion 105 of the bulk-type device isolation layer.

The dielectric pattern 112 r, the first conductive pattern 113 r, thesecond conductive pattern 114 r and the metal silicide pattern 115 r maybe sequentially stacked on the protrusion portion 105 of the bulk-typedevice isolation layer, and thus the connector 192 of the resistorpattern 190 may be positioned on the protrusion portion 105 of thebulk-type device isolation layer. It is possible that the secondconductive pattern 114 r may be arranged on the recess portion 104 ofthe bulk-type device isolation layer and thus the resistor body 191 ofthe resistor pattern 190 may be positioned in the recess portion 104 ofthe bulk-type device isolation layer. The second conductive pattern 114r may be shaped into a line in such a configuration that the secondconductive pattern 114 r may cover an upper surface of the protrusionportion 105 and bottom and sidewalls of the recess portion 104 of thebulk-type device isolation layer. That is, the second conductive pattern114 r may be arranged on an upper surface of the bulk-type deviceisolation layer along a surface profile of the recess and thus theprotrusion portion 105 may be covered with the second conductive pattern114 r and the recess may be partially filled with the second conductivepattern 114 r.

The same dielectric pattern 112, the first conductive pattern 113, thesecond conductive pattern 114 and the metal silicide pattern 115 may bearranged in the cell area 101 a and the peripheral area 101 b of thesubstrate 101. Thus, the same patterns 112 to 115 on the cell area 101 aand the resistor portion 101 b 2 of the peripheral area 101 b may bereferred to as 112 c to 115 c and 112 r to 115 r, respectively,according to the positions at which the patterns 112 to 115 may bearranged on the substrate 101. For example, the dielectric pattern 112 crefers to the dielectric pattern that is arranged in the cell area 101 aand the dielectric pattern 112 r refers to the dielectric pattern thatis arranged on the bulk-type device isolation layer 102 of theperipheral area 101 b of the substrate 101.

A spacer 121 may be positioned on a sidewall of the gate pattern 180 andthe tunnel insulation pattern 110 and the spacer 121 may be exposed to agap space between a pair of neighboring gate patterns 180. An etch stoplayer 122 may be positioned on the spacer 121 and the tunnel insulationpattern 110 in the gap space. A protection pattern 123 may be positionedin the gap space in such a configuration that an upper sidewall of thegate pattern 180 may not be covered with the protection pattern 123.Since the protection pattern 123 may also be arranged across the cellarea 101 a and the peripheral area 101 b of the substrate 101, and thesecond conductive pattern 114 r may also be uncovered with theprotection pattern 123 at the protrusion portion 105 of the bulk deviceisolation layer 102, while the second conductive pattern 114 r in therecess portion 104 may be fully covered with the protection pattern 123.That is, the second conductive pattern 114 r of the resistor body 191may be sufficiently covered with the protection pattern 123 and thesecond conductive pattern 114 r of the connector 192 may be exposed fromthe protection pattern 123.

In the present example embodiment, the recess may have the depth D ofabout 350 Å to about 550 Å. In such a case, the second conductivepattern 114 r may have the stepped portion of about 800 Å to about 1,000Å between the recess portion 104 and the protrusion portion 105 of thebulk device isolation layer 102 since the dielectric pattern 112 r andthe first conductive pattern 113 r may be further positioned under thesecond conductive pattern 114 r at the protrusion portion 105 of thebulk device isolation layer 102.

The metal silicide pattern 115 c of the cell area 101 a may bepositioned on the second conductive pattern 114 c of the gate pattern180 and the metal silicide pattern 115 r of the resistor portion of theperipheral area 101 b may be positioned on the second conductive pattern114 r that may protrude from the protection pattern 123. Thus, the metalsilicide pattern 115 r may be arranged at an upper portion of theconnector 192 of the resistor pattern 190. The metal silicide pattern115 r may be positioned at the upper portion of the connector 192without any electrical effect on the resistor body 191. Thus, a contactresistance Rc of the connector 192 may be sufficiently reduced withoutany deterioration of a sheet resistance of the resistor pattern 190,thereby sufficiently minimizing a resistance variation of the resistorpattern 190 caused by the increase and non-uniformity of the contactresistance Rc of the connector 192.

An insulation interlayer 130 may be positioned on the protection pattern123 and the metal silicide pattern 115 across the cell area 101 a andthe peripheral area 101 b of the substrate 101. The insulationinterlayer 130 may include a plurality of openings (not shown) throughwhich the active regions A may be partially exposed in the cell area 101a and the connector 192 of the resistor pattern 190 may be exposed inthe resistor portion 101 b 2 of the peripheral area 101 b. Underlyingstructures such as the gate pattern 180 and the connector 192 of theresistor pattern 190 may be electrically insulated from upper structuressuch as wiring structures.

A wiring interconnection 140 and a resistor interconnection 150 may bepositioned in openings of the insulation interlayer 130, for example, afirst hole 132 and a second hole 134, respectively. The wiringinterconnection 140 may be electrically connected to the active region Aof the substrate 101 and the resistor interconnection 150 may beelectrically connected to the connector 192 of the resistor pattern 190.For example, the wiring interconnection 140 may include a bit linecontact to make contact with the active region A of the substrate 101disposed adjacent to the SSL of the flash memory device. In the presentexample embodiment, the wiring interconnection 140 and the resistorinterconnection 150 may have substantially the same materials and may beformed by the same process.

For example, the first conductive pattern 113 may comprise carbon-doped(C-doped) polysilicon and the second conductive pattern 114 may comprisephosphor-doped (P-doped) polysilicon. Thus, the underlying conductivestructures may be sufficiently prevented from damage in a heat treatmentfor forming the metal silicide pattern 115 by the C-doped polysiliconpattern and the P-doped polysilicon pattern. In addition, the assemblyof the C-doped polysilicon pattern and the P-doped polysilicon patternmay also prevent the diffusion of the metal silicide to the underlyingstructures.

The wiring interconnection 140 and the resistor interconnection 150 mayinclude low-resistive metals and the metal silicide pattern 115 maycomprise silicide materials of the metal in the wiring interconnection140 and the resistor interconnection 150. For example, the wiringinterconnection 140 and the resistor interconnection 150 may comprisecobalt (Co) or nickel (Ni), the metal silicide pattern 115 may comprisecobalt silicide or nickel silicide.

Although not shown in figures, various wiring structures (notillustrated) may be arranged on the insulation interlayer 130 in such aconfiguration that the wiring interconnection 140 and the resistorinterconnection 150 may make contact with the wiring structures. Apassivation layer (not illustrated) may be further arranged on theinsulation interlayer 130 to cover the wiring structures and insulatingthe wiring structures from surroundings, thereby completing theintegrated circuit device 1000.

According to an example embodiment of the integrated circuit device, theresistor pattern for applying a reference voltage to cell transistorsmay be provided with the bulk-type device isolation layer in such aconfiguration that the resistor body is arranged in the recess of thebulk-type device isolation layer and the connector is arranged aroundthe recess of the bulk-type device isolation layer, so that the resistorpattern may have a stepped portion between the resistor body and theconnector. It is possible that the metal silicide may be arranged at theupper portion of the connector of the resistor pattern. Thus, a contactresistance Rc between the connector and the resistor interconnection maybe sufficiently reduced without any deterioration of a sheet resistanceRs of the resistor body. Accordingly, an electrical resistance of theresistor pattern may be reduced and become stable, and thus a referencevoltage may be applied to the cell transistors with high reliability.

Hereinafter, a method of manufacturing the integrated circuit device ofFIG. 1 will be described in detail with reference to FIGS. 3A to 12C.

FIGS. 3A to 12C are cross-sectional view illustrating a method ofmanufacturing the integrated circuit device of FIG. 1. FIGS. 3A, 4A, . .. and 12A correspond to the cross-sectional view along a line I-I′ ofFIG. 1. FIGS. 3B, 4B, . . . and 12B correspond to the cross-sectionalview along a line II-II′ of FIG. 1. FIGS. 3C, 4C, . . . and 12Ccorrespond to the cross-sectional view along a line III-III′ of FIG. 1.In FIG. 3A to 12C, the same reference numerals will be used to refer tothe same or like parts as those shown in FIG. 1.

Referring to FIGS. 1 and 3A to 3C, the device isolation layer 102 may beformed on the field region F, and the tunnel insulation pattern 110 andthe floating gate pattern 111 may be formed on the active region A ofthe substrate 101 defined by the device isolation layer 102.

The substrate 101 may include a semiconductor substrate, such as awafer, and a plurality of conductive structures may be arranged on theactive region A of the substrate 101 and the conductive structuresdisposed adjacent to each other may be electrically insulated from eachother by the device isolation layer 102. A plurality of the celltransistors may be formed into a matrix shape in the cell area 101 a ofthe substrate 101, and a plurality of the peripheral transistors for adriving circuit and a grounding circuit may be arranged in theperipheral area 101 b of the substrate 101. The driving circuit maygenerate an electric power to drive the cell transistors and thegrounding circuit may provide a potential to electrically ground thecell transistors, for example. The peripheral area 101 b of thesubstrate 101 may include the peripheral circuit portion 101 b 1 inwhich the peripheral transistors may be arranged and the resistorportion 101 b 2 in which the resistor pattern 190 may be positioned. Theresistor pattern 190 may be connected to the driving circuit and controlthe reference voltage applied to the cell transistors.

A tunnel insulation layer (not illustrated) and a floating gate layer(not illustrated) may be sequentially formed on the substrate 101. Amask pattern (not illustrated) may be formed on the floating gate layer,and then the floating gate layer, the tunnel insulation layer and thesubstrate 101 may be sequentially etched off by an etching process usingthe mask pattern, thereby forming the tunnel insulation pattern 110 cand the floating gate pattern 111 c on the active region A and a trenchat the field region F of the substrate 101. The trench may be formedinto a line in the cell area 101 a and the peripheral area 101 b of thesubstrate 101 or into a bulk recess at the resistor portion 101 b 2 ofthe peripheral area 101 b.

A preliminary device isolation layer (not illustrated) may be formed onthe substrate 101 to a sufficient thickness to fill up the trenches ofthe substrate 101 and gap spaces between the neighboring tunnelinsulation patterns and floating gate patterns. Then, an upper portionof the preliminary device isolation layer may be planarized until anupper surface of the floating gate layer may be exposed. Therefore, thepreliminary device isolation layer may remain in the gap space and thetrench, thereby forming the device isolation layer 102 extending in thefirst direction in parallel with the tunnel insulation pattern 110 c andthe floating gate pattern 111 c. The floating gate pattern 111 c and thedevice isolation layer 102 may be formed on the substrate 101simultaneously with each other by a self-aligned process, and thus thedevice isolation layer 102 may be coplanar with the floating gatepattern 111 c.

For example, the tunnel insulation pattern 110 c may include thermaloxide and the floating gate pattern 111 c may include first conductivematerials. Examples of the first conductive materials may include dopedpolysilicon, metal, metal silicide, metal oxide silicide, metal nitridesilicide, etc. These may be used alone or in combinations thereof. Thedevice isolation layer 102 may include one of undoped silicate glass(USG) and oxide deposited through a high density plasma CVD (HDPCVD)process.

While the present example embodiment discloses that the device isolationlayer and the floating gate pattern and the tunnel insulation patternmay be simultaneously formed by the self-alignment process, the deviceisolation layer 102 and the floating gate pattern and the tunnelinsulation pattern may be formed individually or separately from oneanother by respective processes. For example, the device isolation layer102 may be formed in the line-shaped trench at the field region F of thesubstrate 101 and then the tunnel insulation pattern 110 c and thefloating gate pattern 111 c may be formed on the active region A of thesubstrate 101 that may be exposed between the line-shaped deviceisolation layer 102.

Although not illustrated in figures, the tunnel insulation pattern andthe floating gate pattern may also be formed on the active region A ofthe peripheral area 101 b as well as the cell area 101 a of thesubstrate 101. While the device isolation layer 102 may be formed into aline extending along the first direction x in the cell area 101 a,various shapes may be allowable to the device isolation layer 102 in theperipheral area 101 b of the substrate 101. For example, the deviceisolation layer 102 around the peripheral circuit portion 101 b 1 may beformed into a line and the device isolation layer 102 around theresistor portion 101 b 2 may be formed into a single bulk recess.

Referring to FIGS. 1 and 4A to 4C, an inter-gate dielectric layer 112and a first conductive layer 113 may be formed on the floating gatepattern 111 c along a surface profile of the floating gate pattern 111 cof which sidewalls may be partially exposed.

For example, a cell mask pattern (not illustrated) may be formed on thefloating gate pattern 111 c and the device isolation layer 102 in such amanner that the peripheral area 101 b may be covered with the cell maskpattern and the ell area 101 a may be exposed through the cell maskpattern. Then, the device isolation layer 102 of the cell area 101 a maybe partially removed by an etching process using the cell mask patternas an etching mask, and thus an upper surface of the device isolationlayer 102 may be lower than an upper surface of the floating gatepattern 111 c and an upper sidewall of the floating gate pattern 111 cmay be exposed. Thus, the inter-gate dielectric layer 112 may makecontact with the floating gate pattern 111 c on a larger surfacethereof, thereby increasing the dielectric constant of the inter-gatedielectric pattern 112 c.

Since the device isolation layer 102 at the resistor portion 101 b 2 ofthe peripheral area 101 b may not be removed from the substrate 101, theupper surface of the device isolation layer 102 may be higher in theperipheral area 1012 b than in the cell area 101 a of the substrate 101.

For example, when the floating gate pattern 111 c may includepolysilicon and the device isolation layer 102 may include oxide, thedevice isolation layer 102 in the cell area 101 a may be removed by awet etching process using an aqueous hydrogen fluoride (HF) solution asan etchant. The aqueous hydrogen fluoride (HF) solution may have asufficient etching selectivity with respect to the polysilicon and theoxide.

Then, the cell mask pattern may be removed from the floating gatepattern 111 c and the inter-gate dielectric layer 112 and the firstconductive layer 113 may be sequentially formed on the floating gatepattern 111 c and the reduced device isolation layer 102.

The inter-gate dielectric layer 112 may have a dielectric constanthigher than that of the tunnel insulation pattern 110 c. For example,the inter-gate dielectric layer 112 may include a multilayeredoxide/nitride/oxide (ONO) layer in which a first oxide layer, a nitridelayer and a second oxide layer may be stacked and a high-k dielectriclayer comprising high-k materials. Examples of the high-k materials mayinclude aluminum oxide, hafnium oxide, hafnium aluminum oxide, zirconiumoxide, etc. These may be used alone or in combinations thereof. Thefirst conductive layer 113 may comprise carbon-doped polysilicon(C-doped polysilicon).

Referring to FIGS. 1 and 5A to 5C, a first mask pattern 172 may beformed on the first conductive layer 113. The first mask pattern 172 mayhave a first opening 172 a through which the first conductive layer 113corresponding to the SSL may be partially exposed, a second opening 172b through which the first conductive layer 113 at the resistor portion101 b 2 of the peripheral area 101 b may be partially exposed and athird opening (not illustrated) through which the first conductive layer113 at the peripheral circuit portion 101 b 1 of the peripheral area 101b may be exposed. For example, the first mask pattern 172 may include aphotoresist pattern.

Referring to FIGS. 1 and 6A to 6C, the first conductive layer 113 andthe inter-gate dielectric layer 112, which may be exposed through thefirst to third openings, may be partially removed by an etching processusing the first mask pattern 172 as an etching mask. Thus, a buttinghole 182 a communicating with the first opening 172 a may be formed inthe cell area 101 a of the substrate 101 in which a selection transistormay be formed in a subsequent process. A whole surface of the floatinggate pattern may be exposed through the third opening at the peripheralcircuit portion 101 b 1 of the peripheral area 101 b.

Particularly, the second opening 172 b of the first mask pattern 172 maybe formed into a line extending in the first direction x and thus thefirst conductive layer 113 and the inter-gate dielectric layer 112 maybe linearly exposed along the first direction x at the resistor portion101 b 2 of the peripheral area 101 b. Therefore, the device isolationlayer 102 may be linearly exposed at the resistor portion 101 b 2 of theperipheral area 101 b after the removal of the first conductive layer113 and the inter-gate dielectric layer 112. Thereafter, the deviceisolation layer 102 may be further etched off using the first maskpattern as an etching mask, thereby forming the recess portion 104 atthe device isolation layer 102 at the resistor portion 101 b 2 of theperipheral area 101 b. The recess portion 104 of the device isolationlayer 102 may be formed into a line extending in the first direction xcorresponding to the shape of the second opening 172 b. Thus, the deviceisolation layer 102 may include a recess space 182 b communicating withthe second opening 172 b and the residuals of the device isolation layer102 defining the recess space 182 b may relatively protrude from thebottom of the recess portion 104. Therefore, the residuals of the deviceisolation layer 102 except the recess portion 104 may remain withoutbeing etched and thus be formed into the protrusion portion 105. Thatis, the device isolation layer 102 of the resistor portion 101 b 2 mayinclude the recess portion 104 and the protrusion portion 105.

Therefore, the inter-gate dielectric layer 102 and the first conductivelayer 103 may still remain on the protrusion portion 105 of the deviceisolation layer at the resistor portion 101 b 2 and the recess portion104 of the device isolation layer 102 may be exposed to surroundings.That is, the protrusion portion 105 may be covered with the inter-gatedielectric layer 102 and the first conductive layer 103 and the recessportion 104 may be exposed to surroundings.

In the present example embodiment, the recess portion 104 may have adepth d of about 350 Å to about 550 Å from the upper surface of thedevice isolation layer 102.

Since the floating gate pattern 111 c may have sufficient etchingselectivity with respect to the device isolation layer 102, the floatinggate pattern 111 c exposed through the first opening 172 a and the thirdopening may be hardly etched off in the etching process for forming therecess space 182 b. However, when the depth d of the recess portion 104may be over about 550 Å, the floating gate pattern 111 c at the cellarea 101 a and the peripheral circuit portion 101 b 1 may tend to beetched off simultaneously with the device isolation layer 102 of theresistor portion 101 b 2. Thus, the depth d of the recess portion 104may be smaller than about 550 Å. In addition, when the depth of therecess portion 104 may be less than about 350 Å, the difference betweenthe protrusion portion 105 and the recess portion 104 may be so smallthat the subsequent silicidation process may also be performed to theresistor body 191 in the recess portion 104. That is, the resistor body191 may tend to be under the silicidation process when the depth of therecess portion is less than about 350 Å. For those reasons, the depth dof the recess portion 104 may be in a range of about 350 Å to about 550Å.

Accordingly, when the inter-gate dielectric layer 112 and the firstconductive layer 113 may have the thickness of about 150 Å to about 300Å, a stepped difference d2 between an upper surface of the firstconductive layer 113 and the bottom of the recess portion 104 may be ina range of about 800 Å to about 1000 Å. The stepped difference d2 may bevaried in accordance with the thickness of the inter-gate dielectriclayer 112 and the first conductive layer 113, as would be known to oneof the ordinary skill in the art.

Referring to FIGS. 1 and 7A to 7C, the first mask pattern 172 may beremoved from the first conductive layer 113 and a second conductivelayer 114 may be formed on the first conductive layer 113.

For example, the second conductive layer 114 may be formed on the firstconductive layer 113 to a sufficient thickness to fill up the buttinghole 182 a and the recess space 182 b. Thereafter, an upper surface ofthe second conductive layer 114 may be planarized.

Therefore, the second conductive layer 114 may make direct contact withthe floating gate pattern 111 c through the butting hole 182 a for astring selection transistor. The second conductive layer 114 may beformed on the first conductive layer 113 in the cell area 101 a exceptfor the area at which the string selection transistor is to be formed.Since the whole surface of the floating gate pattern 111 may beuncovered at the peripheral circuit portion 101 b 1 of the peripheralarea 101 b, the second conductive layer 114 may be formed on the wholesurface of the floating gate pattern 111. In the resistor portion 101 b2 of the peripheral area 101 b of the substrate 101, the secondconductive layer 114 may be formed on the resistor portion of theperipheral area of the substrate 101 along a surface profile of therecess portion 104. Thus, the first conductive layer 113 and theinter-gate dielectric layer 112 on the protrusion portion 105 and thebottom and sidewalls of the recess portion 104 may be covered with thesecond conductive layer 114. The second conductive layer 114 may have astepped difference D corresponding to the stepped difference d2 as thedevice isolation layer 102 of the resistor portion 101 b 2.

For example, the second conductive layer 114 may include phosphor-dopedpolysilicon (P-doped polysilicon). The second conductive layer 114 mayimprove conductivity of an upper portion of the stack gate structuresuch as the control gate electrode for a flash memory device in the cellarea 101 a and may prevent the silicide materials from being diffusedinto downwards in a subsequent silicidation process.

The second conductive layer 114 may be uniformly formed on a wholesurface of the substrate 101 and thus the stepped difference D of thedevice isolation layer 102 of the resistor portion 102 b 2 may betranscribed into the second conductive layer 114 at the resistor portion101 b 2.

Referring to FIGS. 1 and 8A to 8C, a second mask pattern 174 may beformed on the second conductive layer 114 and an etching process usingthe second mask pattern 174 as an etching mask may be performed on theresultant substrate, thereby forming a preliminary gate pattern 180 aand a preliminary resistor pattern 190 a respectively on the cell area101 a and the resistor portion 101 b 2 of the peripheral area 101 b ofthe substrate 101.

For example, the second mask pattern 174 may include a fourth opening(not illustrated) through which the second conductive layer 114 of thecell area 101 a may be exposed, a fifth opening (not illustrated)through which the second conductive layer 114 of the peripheral circuitportion 101 b 1 of the peripheral area 101 b may be exposed and a sixthopening (not illustrated) through which the second conductive layer 114of the resistor portion 101 b 2 may be exposed. The fourth opening maybe formed into a trench extending in the second direction ysubstantially perpendicular to the line-shaped active region A and thefifth opening may be formed into a trench extending in a givendirection. The sixth opening may be formed into a trench extending inthe first direction x.

The second mask pattern 174 may include a material having etchingselectivity with respect to the second conductive layer 114 such assilicon nitride. The second mask pattern 174 may include a gate mask oran assembly of the gate mask and a photo mask on the gate mask that maycover the gate pattern in a subsequent process.

The second conductive layer 114, the first conductive layer 113, theinter-gate dielectric layer 112 and the floating gate pattern 111 may besequentially etched off by an etching process using the second maskpattern 174 as an etching mask, thereby forming the preliminary gatepattern 180 a on the active region A and the preliminary resistorpattern 190 a on the resistor portion 101 b 2.

In the cell area 101 a of the substrate 101, the second conductive layer114, the first conductive layer 113, the inter-gate dielectric layer 112and the floating gate pattern 111 c may be sequentially removed from thesubstrate 101 in such a manner that the tunnel insulation pattern 110 cmay be exposed along the second direction y. Thus, the floating gatepattern 111 c may be node-separated into a plurality of floating gatesby the cell in the cell area 101 a of the substrate 101. Thus, theline-shaped floating gate pattern 111 c may be separated into thefloating gates at each cell of the cell area 101 a and may be arrangedinto a matrix shape and regularly spaced apart from one another.Further, the inter-gate dielectric layer 112, the first conductive layer113 and the second conductive layer 114 may be linearly removed alongthe second direction y, thereby forming the line-shaped dielectricpattern 112 c and the first and second line-shaped conductive patterns113 c and 114 c that may extend along the second direction y in the cellarea 101 a. Thus, the floating gate, the dielectric pattern 112 c andthe first and the second conductive patterns 113 c and 114 c may besequentially stacked at each cell, thereby forming the preliminary gatepattern 180 a for a cell transistor.

In the peripheral circuit portion 101 b 1 of the peripheral area 101 bof the substrate 101, the second conductive layer 114 and the floatinggate pattern 111 may be sequentially removed from the substrate 101 byan etching process using the second mask pattern 174 as an etching maskin such a manner that the tunnel insulation pattern 110 may be exposedalong a given direction. Thus, the floating gate pattern 111 may benode-separated into a plurality of floating gates for a peripheraltransistor. The floating gates may also be spaced apart by a gapdistance in a given direction. Thus, the floating gate and the secondconductive pattern 114 may be sequentially stacked at each cell of theperipheral circuit portion 101 b 1 of the peripheral area 101 b of thesubstrate 101, thereby forming the preliminary gate pattern 180 a in theperipheral circuit portion 101 b 1 for a peripheral circuit transistor.

In the resistor portion 101 b 2 of the peripheral area 101 b of thesubstrate 101, the second conductive layer 114, the first conductivelayer 113 and the inter-gate dielectric layer 112 may be sequentiallyremoved from device isolation layer 102 of the resistor portion 101 b 2in such a manner that the device isolation layer 102 adjacent to therecess portion 104 may be exposed along the first direction x. Thus, thesecond mask pattern 174 may remain on the second conductive layer 114 onthe recess portion 104 and the protrusion portion 105 in the firstdirection, thereby forming the preliminary resistor pattern 190 a on theresistor portion 101 b 2 of the peripheral area 101 b. The inter-gatedielectric layer 112 and the first conductive layer 113 may be removedfrom the substrate 101 along the first direction and thus just merely onthe protrusion portion of the device isolation layer 102 of the resistorportion 101 b 2, thereby forming the dielectric pattern 112 r and thefirst conductive pattern 113 r. The second conductive layer 114 may beformed into a line across the protrusion portion 105 and the recessportion 104 along the first direction x, thereby forming the secondconductive pattern 114 r.

The preliminary resistor pattern 190 a may include a preliminaryresistor body 191 a corresponding to the second conductive pattern 114 rin the recess portion 104 and a preliminary connector 192 a having thedielectric pattern 112 r and the first and the second conductivepatterns 113 r and 114 r that may be stacked on the protrusion portionof the device isolation layer 102 of the resistor portion 101 b 2.

Thereafter, a spacer 121 may be formed on sidewalls of the preliminarygate pattern 180 a, and an etch stop layer 122 may be formed on thespacer 121. The spacer 121 may include silicon oxide having goodinsulative characteristics and the etch stop layer 122 may comprisesilicon nitride or silicon oxynitride.

Referring to FIGS. 1 and 9A to 9C, a protection pattern 123 may befilled up into a gap space between the neighboring preliminary gatepatterns 180 a and into the recess space 182 b in which the preliminaryresistor pattern 190 a may be formed.

For example, a protection layer (not illustrated) may be formed on thesubstrate 101 to a sufficient thickness to fill up the gap space betweenthe neighboring preliminary gate patterns 180 a and the recess space 182b including the preliminary resistor pattern 190 a. Then, an upperportion of the protection layer may be planarized by a planarizationprocess until the second mask pattern 174 on the preliminary gatepattern 180 a and the preliminary resistor pattern 190 a may be exposed.

Therefore, the protection layer may remain in the gap space and therecess space 182 b in such way that an upper surface of the second maskpattern 174 may be coplanar with the upper surfaces of the preliminarygate pattern 180 a and the preliminary resistor pattern 190 a, therebyforming the protection pattern 123 on the substrate 101.

For example, the protection layer may include a material having goodgap-fill and insulative characteristics, such as tetra ethylortho-silicate (TEOS) deposited by plasma enhanced CVD process to formplasma enhanced tetra ethyl ortho-silicate (PETEOS). Thus, the gap spacebetween the preliminary gate patterns 180 a and the recess space 182 bof the recess portion 104 may be sufficiently filled up with theprotection pattern 123 with good electrical insulation fromsurroundings. The planarization process may include a chemicalmechanical polishing (CMP) process and an etch-back process.

Referring to FIGS. 1 and 10A to 10C, the protection pattern 123 and thesecond mask pattern 174 may be partially removed, thereby exposing thesecond conductive pattern 114 c of the preliminary gate pattern 180 aand the second conductive pattern 114 r of the preliminary resistivepattern 190 a.

For example, an upper portion of the protection pattern 123 and the etchstop layer 122, the second mask pattern 174 and an upper portion of thespacer 121 may be removed from the substrate 101 in such a degree thatan upper portion of the second conductive pattern 114 may be exposed atthe active region A and the resistor portion 101 b 2 of the preliminaryarea 101 b of the substrate 101.

A planarization process and/or etching process may be used for removingthe protection pattern 123, the etch stop layer 122, the second maskpattern 174 and the spacer 121. The planarization process may include achemical mechanical polishing (CMP) process, a chemically enhancedpolishing (CEP) process and an etch-back process. The etching processmay include dry and wet etching processes.

The gap space between the neighboring preliminary gate pattern 180 a maystill be filled with the protection pattern 123, the etch stop layer 122and the spacer 121, and the recess space 182 b may still be filled withthe protection pattern 123, the etch stop layer 122 and the second maskpattern 174. Thus, the second conductive pattern 114 c formed on thepreliminary gate pattern 180 a and on the preliminary connector 192 amay protrude from the planarized protection pattern 123, the etch stoplayer 122 and the spacer 121. Further, the second conductive pattern 114r formed on the bottom of the recess portion 104 may still be coveredwith the protection pattern 123, the etch stop layer 122 and the secondmask pattern 174.

Referring to FIGS. 1 and 11A to 11C, a metal silicide pattern 115 may beformed on the exposed second conductive pattern 114.

For example, a metal layer (not illustrated) may be formed on the wholesubstrate 101 along a surface profile of the protruded second conductivepattern 114, and thus the metal layer may be formed on the protectionpattern 123, the etch stop layer 122 and the spacer 121 while coveringthe protruded second conductive pattern 114 c in the active region A ofthe substrate 101. The metal layer may also be formed on the protectionpattern 123, the etch stop layer 122 and the second mask pattern 174while covering the protruded second conductive pattern 114 r in theresistor portion 101 b 2 of the peripheral area 101 b of the substrate101.

For example, the metal layer comprise low-resistive materials such ascobalt (Co), nickel (Ni), tungsten (W), aluminum (Al), titanium (Ti) andtantalum (Ta).

A heat treatment may be performed on the metal layer. Thus, a silicidereaction may be initiated between the metal and the second conductivepattern 114 due to the heat. Since the second conductive pattern 114 mayinclude polysilicon and the protection pattern 123, the etch stop layer122, the spacer 121 and the second mask pattern 174 may include oxide ornitride, the silicidation reaction may be processed just merely at theupper portion of the second conductive pattern 114. For example, theheat treatment may be performed by rapid thermal process (RTP).Accordingly, the exposed second conductive pattern 114 may react withthe metal layer by the silicidation process, thereby forming the metalsilicide pattern 115 c on the preliminary gate pattern 180 a in theactive region A and the metal silicide pattern 115 r on the preliminaryconnector 192 a in the resistor portion of the peripheral area 101 b.

Accordingly, the preliminary gate pattern 180 a may be formed into thegate pattern 180 in which the floating gate pattern 111 c, thedielectric pattern 112 c, the first and the second conductive pattern113 c and 114 c and the metal silicide pattern 115 c may be stacked onthe active region A of the substrate 101. Further, the preliminaryconnector 192 a of the resistor portion 101 b 2 may be formed into theconnector 192 in which the dielectric pattern 112 r, the first and thesecond conductive patterns 113 r and 114 r and the metal silicidepattern 115 r on the protrusion portion of the device isolation layer102 in the resistor portion 101 b 2 of the peripheral area 101 b. Thepreliminary resistor body 191 a corresponding to the second conductivepattern 114 r at the bottom of the recess portion 104 may be coveredwith the protection pattern 123, the etch stop layer 122 and the secondmask pattern 174, and thus the preliminary resistor body 191 a may beprotected from the silicidation. Accordingly, the electric resistance ofthe preliminary resistor body 191 a may not be deteriorated by thesilicidation process. The preliminary resistor body 191 a may be formedinto the resistor body 191 after the heat treatment for the silicidationprocess.

Thereafter, the residuals of the metal layer that may not be processedwith the silicidation process may be removed, and thus the protectionpattern 123, the etch stop layer 122, the spacer 121 and the second maskpattern 174 may be exposed again.

The first and the second conductive patterns 113 c and 114 c and themetal silicide pattern 115 c in the cell area 101 a may extend in thesecond direction y, thereby forming the SSLs, WLs and GSLs of the flashmemory device. The dielectric pattern 112 r, the first and the secondconductive patterns 113 r and 114 r and the metal silicide pattern 115 rmay be formed into the connector 191 of the resistor pattern 190 at theprotrusion portion 105 of the device isolation layer 102 at the resistorportion 101 b 2 of the peripheral area 101 b. In addition, the secondconductive pattern 114 r at the bottom of the recess portion 104 may beformed into the resistor body 192 of the resistor pattern 190.

Referring to FIGS. 1 and 12A to 12C, an insulation interlayer 130 may beformed on the metal silicide pattern 115 and the protection pattern 123and the wiring interconnection 140 and the resistor interconnection 150may be formed through the insulation interlayer 130.

For example, a preliminary insulation interlayer (not illustrated) maybe formed on the substrate 101 including the metal silicide pattern 115and the protection pattern 123 to a sufficient thickness to cover theprotection pattern 123, the etch stop layer 122 and the second maskpattern 174 and then an upper portion of the preliminary insulationinterlayer may be planarized.

Then, a plurality of contact holes may be formed through the insulationinterlayer 130. A first hole 132 may be formed through the insulationinterlayer 130 in the active region A of the substrate 101 and thus theprotection pattern 123 may be partially exposed through the first hole132 in the active region A. A second hole 134 may be formed through theinsulation interlayer 130 at the resistor portion 101 b 2 of theperipheral area 101 b of the substrate 101. Thus, the metal silicidepattern 115 r of the connector 192 may be exposed through the secondhole 134. The protection pattern 123 and the tunnel insulation layer 110c under the protection pattern 123 exposed through the first hole 132may be etched off, thereby forming a contact hole 123 a through whichthe active region A of the substrate 101 may be partially exposed. Insuch a case, the etch stop layer 122 may prevent the over etchingagainst the substrate 101.

A conductive pattern may be filled into the first hole 132 and thecontact hole 123 a communicating with the first hole by consecutiveprocesses of deposition and planarization, thereby forming the wiringinterconnection 140. Further, conductive pattern may also be filled intothe second hole 134 simultaneously with the wiring interconnection 140,thereby forming the resistor interconnection 150.

The conductive pattern may comprise the same metal as the metal silicidepattern 115. For example, when the metal silicide pattern 115 maycomprise cobalt silicide, the wiring interconnection 140 and theresistor interconnection 150 may comprise cobalt (Co). In the presentexample embodiment, the wiring interconnection 140 may include a bitline contact plug adjacent to the string selection transistor.

Accordingly, since the resistor interconnection 150 and the connector192 of the resistor pattern 190 may include the same metal, the contactresistance Rc between the resistor interconnection 150 and the connector192 may be sufficiently reduced. Therefore, the resistance of theresistor pattern 190 may be sufficiently stable and reliable and thusthe reference voltage may be stably applied to the cell transistors.

Thereafter, additional wring structures (not illustrated) may be formedon the insulation interlayer 130 and a passivation layer (notillustrated) may be formed on the additional wiring structure, tothereby manufacturing the non-volatile memory device 1000.

FIG. 13 is a view illustrating an integrated circuit system includingthe integrated circuit device of FIG. 1.

Referring to FIG. 13, an integrated circuit system 2000 in accordancewith an example embodiment of the present inventive concept may includethe integrated circuit device 1000 illustrated in FIG. 1 and an externalmicroprocessor 1100 to control the integrated circuit device 1000.

The integrated circuit device 1000 may include a plurality of celltransistors arranged as a matrix shape in a memory cell area 400 and aplurality of peripheral transistors arranged in a peripheral area aroundthe memory cell area 400. The cell transistors may be operated by theperipheral transistors. For example, an address decoder 500, row andcolumn decoders 600 and 700, a control circuit 800 and input/outputcircuits 900 may be provided around the memory cell area 400. Theresistor pattern 900 of an example embodiment of the present inventiveconcept may be provided with the control circuit 800 and theinput/output circuit 900, and thus the connector 192 including the metalsilicide at an upper portion thereof may be positioned relatively higherthan the resistor body 191 by a stepped portion between the connector192 and the resistor body 191. The metal silicide of the connector 191may have the same metal as the resistor interconnection, and thus thecontact resistance Rc of the resistor pattern 190 and the resistorinterconnection may be minimized and the reference voltage may beapplied to the cell transistors with high reliability in the integratedcircuit system 2000.

The integrated circuit device 1000 may be controlled by a microprocessor1100. The microprocessor 1100 may applies various control signals suchas an address signal and input/output signals to the integrated circuitdevice 1000 and thus various data may be communicated with theintegrated circuit device 1000 by the microprocessor 1100.

Additional circuit devices and signals may be further provided with theintegrated circuit system 2000 in accordance with the systemrequirements of the integrated circuit system 2000.

FIG. 14 is a view illustrating an electronic instrument including theintegrated circuit system of FIG. 13.

Referring to FIG. 14, an electronic instrument 3000 in accordance withan example embodiment of the present inventive concept may include adata processor 2100, an input console 2200, an output console 2300 and adata storing console 2400. The data processor 2100 may include a memoryunit 2110 having the integrated circuit system illustrated in FIG. 13and a control unit 2120 for controlling the memory unit 2110.

The memory unit 2110 may include the integrated circuit systemillustrated in FIG. 13, and thus the reference voltage may be stablyapplied to the cell transistors with high reliability and the celltransistors may be stably operated in data programming, erasing andreading mode. While the present example embodiment discloses a NANDflash memory device as the memory unit 2110, any other memory devicessuch as NOR flash memory device and other memory devices including theresistor pattern 190. The control unit 2120 may include a digital signalprocessor such as a microprocessor, a digital signal processor and amicro controller. The control unit 2120 may control the memory unit 2120to communicate data signals with the input console 2200, the outputconsole 2300 and the data storing console 2400.

While the memory unit 2110 and the control unit 2120 may be individuallymanufactured independently from each other and may be electricallyconnected to each other, any other modifications known to one of theordinary skill in the art may also be allowable for the data processor2100. For example, the memory unit 2110 and the control unit 2120 may beassembled into a single data process package. In such a case, the dataprocessing time may be reduced between the memory unit 2110 and thecontrol unit 2120.

The input console 2200 and the output console 2300 may include a keypad,keyboard, a monitor and a flat panel display device. In addition, anyother user interface may be further provided with the electronicinstrument 3000 such as a MODEM, a graphic driver card and an additionalstoring console.

The electronic instrument 3000 may include a computer system such as adesk top computer, a lap-top computer and a tablet computer and aportable electronic device and a wireless communication device such as amobile phone including as a cellular phone and a smart phone, a PDA, adigital music player and an interface protocol for communication.

According to the example embodiments of the present inventive concept,the recess portion may be formed on the bulk-type device isolation layerat the resistor portion of the peripheral area of the substrate and theresistor pattern may be provided with the bulk-type device isolationlayer in such a configuration that the resistor body is positioned atthe bottom of the recess portion and the connector having the metalsilicide pattern at an upper portion thereof is positioned on thesurface of the bulk-type device isolation layer around the recessportion consecutively to the resistor body. Thus, the connector and theresistor body may have a stepped portion therebetween due to the recessportion of the bulk-type device isolation layer. The metal silicidepattern of the connector may include the same metal as the resistorinterconnection and thus the contact resistance between the resistorpattern and the resistor interconnection may be minimized. Therefore,the variation of the contact resistance may be reduced withoutdeterioration of the sheet resistance of the resistor body and thus theelectric resistance of the wiring pattern 190 may become stable. As aresult, the reference voltage may be stably applied to the celltransistors with high reliability.

Although a few embodiments of the present general inventive concept havebeen shown and described, it will be appreciated by those skilled in theart that changes may be made in these embodiments without departing fromthe principles and spirit of the general inventive concept, the scope ofwhich is defined in the appended claims and their equivalents.

What is claimed is:
 1. An integrated circuit device comprising: asubstrate having an active region defined by a device isolation layer; aresistor pattern formed on the device isolation layer, the resistorpattern including a resistor body positioned in a recess portion of thedevice isolation layer and at least a connector making contact with theresistor body and positioned on the device isolation layer around therecess portion, the connector having a metal silicide pattern havingelectric resistance lower than that of the resistor body at an upperportion thereof; a gate pattern formed on the active region of thesubstrate, the gate pattern including the metal silicide pattern at anupper portion thereof; and a resistor interconnection making contactwith the connector of the resistor pattern.
 2. The integrated circuitdevice of claim 1, wherein the connector includes a stack structure inwhich a dielectric pattern, a first conductive pattern, a secondconductive pattern and the metal silicide pattern are sequentiallystacked and the resistor body includes the second conductive pattern. 3.The integrated circuit device of claim 2, wherein the first conductivepattern includes carbon (C)-doped polysilicon and the second conductivepattern includes phosphor (P)-doped polysilicon.
 4. The integratedcircuit device of claim 2, wherein the second conductive pattern iscontinuously arranged across the resistor body and the connector and theconnector and the resistor body has a stepped portion of about 800 Å toabout 1,000 Å.
 5. The integrated circuit device of claim 2, wherein thegate pattern includes a tunnel insulation layer, a floating gatepattern, the dielectric pattern, the first and the second conductivepatterns that are sequentially stacked on the cell area of thesubstrate.
 6. An integrated circuit device, comprising: one or moredevice isolation layers formed on a cell area and a peripheral area of asubstrate; a resistor pattern having a resistor body having a firstelectric resistance and a connector having a second electric resistancelower than the first electric resistance, formed on the device isolationlayers of a resistor portion of the peripheral area of the substrate;and a resistor interconnection formed to contact the connector of theresistor pattern to reduce a contact resistance therebetween.
 7. Theintegrated circuit device of claim 6, wherein one or more gate patternsare formed on active regions of the cell area of the substrate, and thedevice isolation layers are formed in field regions of the cell areabetween the adjacent active regions.
 8. The integrated circuit device ofclaim 7, wherein a floating gate pattern of the gate pattern is formedto be disposed between the device isolation layers such that an upperportion of the floating gate pattern of the gate pattern is exposed froman upper portion of one or more the device isolation layers.
 9. Theintegrated circuit device of claim 6, wherein a recess portion and aprotrusion portion are formed in the respective device isolation layerssuch that the resistor body is on the recess portion and the protrusionportion and the connector ids formed on the protrusion portion to have adepth of recess with the resistor body in the recess portion.